FIG. 1 illustrates, in block diagram form, integrated circuit memory 10 in accordance with the prior art. Integrated circuit memory 10 includes memory array 12, row address buffers 13, row predecoders 14, column address buffers 15, column predecoders 16, row select 17, write drivers 18, column logic 19, latch/comparator 20, input data registers 21, match logic circuit 22, a plurality of regular sense amplifiers including sense amplifiers 23, 24, and 25, and a plurality of match sense amplifiers including match sense amplifiers 26, 27, and 28.
Integrated circuit memory 10 is a conventional synchronous static random access memory (SRAM) having a plurality of memory cells organized in rows and columns. The memory cells are coupled at intersections of the rows and columns. A row includes a word line and all of the memory cells coupled to the word line. A column includes a bit line pair and all of the memory cells coupled to the bit line pair.
A write cycle of integrated circuit memory 10 is initiated by asserting a write enable signal labeled "W*" as a logic low. Note that an asterisk (*) after a signal name indicates that the signal is a logical complement of a signal having the same name but lacking the asterisk (*). During a first clock cycle of a clock signal labeled "CLK", input data signals labeled "D.sub.IN " are latched in data registers 21, row address signals labeled "ROW ADDRESS" are supplied to row address buffers 13, and column address signals labeled "COLUMN ADDRESS" are supplied to column address buffers 15. Row predecoders 14 and column predecoders 16 decode and latch the address signals on the first clock cycle. During a second clock cycle, the predecoded signals are latched and compared by latch/comparator 20 and provided to column logic 19 and to row select 17 to enable a word line and select a bit line pair to receive the input data signals. Input data signals D.sub.IN are written to a selected memory cell of memory array 12 using write drivers 18. A memory cell located at the intersection of the selected word line and bit line pair receives a differential data signal via the bit line pair corresponding to input data signal D.sub.IN. During successive write cycles, new input data signals D.sub.IN can be latched in input data registers 21 on every clock cycle.
A read cycle is initiated by negating write enable signal W* as a logic high. In response to the address signals selecting a bit line pair and a word line, a memory cell located at the intersection of the word line and the bit line pair provides a relatively small differential voltage to the bit line pair. A select signal labeled "ASEL" enables the plurality of regular sense amplifiers and the relatively small differential voltage is sensed and amplified by one of sense amplifiers 23, 24, or 25 via column logic 19, and a corresponding data signal labeled "D0", "D1", or "DN" is provided to a read global data line labeled "RGDL0", "RGDL1", or "RGDLN", respectively, where N is an integer.
If a read cycle follows a write cycle at the same address, commonly known as a "read-after-write", data is read from input data registers 21 rather than from memory array 12, because the requested data has not yet been written to memory array 12. To determine when there is a read-after-write, latch/comparator 20 compares the new row and column addresses being accessed to a previous address, if there is a match, match logic circuit 22 provides a match signal labeled "MATCH" to enable each of the plurality of match sense amplifiers. Select signal ASEL is negated as a logic low to deselect the plurality of sense amplifiers 23, 24, and 25. Data is provided to the plurality of match sense amplifiers 26, 27, and 28 from input data registers 21. The plurality of match sense amplifiers are connected to a plurality match global data lines labeled "MGDL0", "MGDL1", and "MGDLN" and provide match data signals labeled "LD0", "LD1", and "LDN", corresponding to input data signals D.sub.IN. Match data signals LD0, LD1, and LDN are multiplexed with data signals D0, D1, or DN (not shown), and the data signals are supplied to output circuitry (not shown), such as output buffers and/or registers.
In integrated circuit memories having both read global data lines and match global data lines, the surface area required to implement the integrated circuit memory may be significantly increased if the data organization, or word width of the integrated circuit memory, is very large. For example, an integrated circuit memory having a word width of 18 bits would require 18 read global data lines and 18 match global data lines. Also, the need to multiplex the match data signals with the regular data signals adds additional complexity to the back end of the memory. In addition, the regular sense amplifiers are generally not disabled during a read-after-write at the same address, causing increased power consumption.